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| Title | Parallel Architecture for Signature Analyzer in LSI Self-Testing (in Japanese) |
|---|---|
| Authors | 松嶋智子 、松嶋敏泰 、平澤茂一 |
| Released Year | 1996 |
| Format | Conference |
| Category | Others |
| Jounal Name | |
| Jounal Page | vol.96, no.21, pp.85-92 |
| Published Year | 1996 |
| Published Month | 4 |
| Abstract （English） |
Several kinds of LFSR-based signature analyzers have been proposed for LSI built-in self test. MLFSR, which has been proposed for multiple output CUT by Pradhan et al., has the possibility to achieve the better aliasing probability than other schemes such as the multiple MISR scheme with comparable hardware complexity. The only problem with this scheme is that the hardware complexity becomes larger than propotionally as δ increases, where δ is the number of parallel signals inputted into MLFSR, and so MLFSR is not adequate for testing CUTs with large number of output signals. In this report, we propose a parallel architecture for signature circuits applicable to such CUTs. This architecture allows Hδ bits to be processed in parallel, where H can be chosen as an arbitrary integer. It is shown that the complexity for the parallel circuit, with Hδ input, signals is much smaller than that for a parallel opereation of H converntional circuits with δinput signals. |
| Note （English） |
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| Manuscript | |
| Presentation |
