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| Title | A Study on Parallel Encoder and Decoder for Cyclic Codes (in Japanese) |
|---|---|
| Authors | 松嶋智子 、松嶋敏泰 、平澤茂一 |
| Released Year | 1995 |
| Format | Conference |
| Category | Channel coding |
| Jounal Name | |
| Jounal Page | vol.95, no.347, pp.23-28 |
| Published Year | 1995 |
| Published Month | 11 |
| Abstract （English） |
In this paper, a parallel encoder and decoder architecture for cyclic codes is presented. This architecture can decrease encoding and decoding time 1/H(H > 1) compared to conventional codec, where H is the number of symbols processed in parallel. As an example, we investigate hardware complexity for a (255,251) Reed-Solomon code over GF(2^8). It is shown that hardware complexity for a set of parallel encoder and decoder is much smaller than that for a parallel operation of H conventional sets. |
| Note （English） |
1 |
| Manuscript | |
| Presentation |
